VLSI Design for Testability - DFT FreshersMNC
Skills : good ability
Experience Required : Freshers
Job Location : Chennai
Job Description :
VLSI Design for Testability - DFT
Location : Chennai
Good knowledge of Hierarchical scan synthesis with :
Handle module level scan insertion.
Handle device scan insertion with multiple clock domains
Able to do Block/ Device level pattern generation and simulations.
Scan interleaved with memory bist patterns gen and validation.
Device level transition delay testing with multiple clocks, handling exceptions.
Able to do Sequential ATPG with RAMs and latches, coverage analysis.
Path Delay tests, delay coverage analysis.
Excellent knowledge on usage of ATPG tool.-
Able to do Silicon debug and diagnostics
Delay tests using PLL, silicon debug and diagnostics.
Good knowledge of On-chip scans compression or bist techniques and test time reduction.
Memory BIST integration in SoC and verification, selecting the optimal mem.
Job Type: Full-time
work: 1 year (Required)
Walkin Date : 04/13/2018 - 04/18/2018
Walkin Time : 09:00 a.m - 02:00 p.m
Walkin Venue : Login to View Venue Details
Job Posted on : 12/04/2018